A practical engineering reference covering physics, charge balance, device structures, switching behaviour, figures of merit, packages, topologies, manufacturing, reliability and selection.
A conventional high-voltage silicon MOSFET needs a lightly doped drift region to sustain blocking voltage. That creates a fundamental trade-off between voltage rating and conduction resistance. A superjunction replaces the conventional drift region with alternating charge-balanced P and N columns. Under blocking conditions the columns deplete laterally, reshaping the electric field and permitting a more heavily doped conduction path.
The practical performance depends strongly on compensation between adjacent P and N regions. Imperfect balance changes breakdown voltage, dynamic behaviour and process margin.
The P pillars alter the depletion and electric-field distribution, allowing a lower-resistivity N region while maintaining the required blocking capability.
Superjunction architecture pushes specific on-resistance beyond the conventional planar silicon trade-off, particularly in high-voltage classes.
| Parameter | What it tells you | Why it matters |
|---|---|---|
| VDS / BV | Drain-source blocking capability | Must cover bus voltage plus transient margin and topology-specific stress. |
| RDS(on) | On-state resistance at specified VGS and temperature | Drives conduction loss and thermal rise; compare under equivalent test conditions. |
| Qg | Total gate charge | Affects gate-drive loss and switching speed. |
| Qgd | Gate-drain / Miller charge | Strongly influences voltage transition and driver requirements. |
| Eoss / Coss | Output capacitance / stored energy | Important in hard and soft switching, especially high-frequency PFC and resonant converters. |
| Qrr / trr | Body-diode reverse recovery | Important in bridge and commutation paths; affects loss, EMI and device stress. |
| dv/dt / di/dt | Dynamic ruggedness | Helps determine how the device behaves during fast switching and transient events. |
| EAS / UIS | Avalanche capability under defined test conditions | Useful for evaluating transient energy tolerance; never treat it as unlimited operating energy. |
| RθJC / RθJA | Thermal resistance | Connects device loss to junction temperature and heatsink/package design. |
Common switching/conduction trade-off indicator. Lower can indicate a better combination, but test conditions and topology still matter.
Useful for considering stored capacitive energy alongside conduction resistance in hard-switching applications.
Highlights the conduction-versus-Miller-charge trade-off relevant to fast switching.
Technology-level metric related to silicon utilization and power density.
Repeated epitaxial growth and column formation can provide charge-balanced structures with controlled vertical dimensions.
Deep-trench approaches form the P/N structure with different process flows and can support high-density architectures.
Column depth, width, doping and charge balance are critical manufacturing variables. Real-world performance therefore reflects process maturity as well as circuit design.
Focus on Eoss, Qgd, Qg, turn-on/turn-off loss, dv/dt, di/dt and EMI. PFC is a major use case.
Zero-voltage switching can reduce turn-on loss, shifting attention toward output capacitance, gate charge, diode behaviour and conduction loss.
Body-diode reverse recovery and circuit parasitics can strongly influence overshoot, loss and EMI.
For high-frequency power conversion, electrical and thermal parasitics of the package can materially affect system behaviour. Common packages include TO-220, TO-247, D2PAK, PowerFLAT, TOLL, TOLL/Kelvin-source variants, QDPAK and other surface-mount formats.
Separates the gate-drive return from the high-current source path to reduce common-source inductance effects.
Moves heat extraction toward the top of the package for dense power designs.
Shorter current paths can reduce parasitics and improve thermal density when the PCB and assembly are designed accordingly.
TO-220/TO-247 remain widely used where mechanical robustness and heatsink mounting are priorities.
High-voltage boost stages in AC-DC supplies.
Resonant server, telecom and consumer power supplies.
On-board chargers and charging power conversion.
PV inverters and auxiliary conversion stages.
High-density AC-DC and server power.
LED drivers and other high-voltage power supplies.
Power conversion stages where silicon SJ remains attractive in appropriate voltage/power ranges.
Welders, automation supplies and motor/inverter systems.
VDS margin · ID · RDS(on) at temperature · VGS · Qg/Qgd · Coss/Eoss · Qrr/trr · avalanche · SOA.
Package · RθJC · mounting · PCB copper · heatsink · junction-temperature limit · transient thermal impedance.
Lifecycle · qualification · PPAP/AEC where relevant · second source · lead time · distributor stock · package availability.